This invention relates generally to semiconductor devices and methods of manufacturing the same, and more particularly to devices such as Metal Oxide Semiconductor (MOS) transistors, Insulated Gate Bipolar Transistors (IGBTs) and MOS-gated conductivity modulated devices including MOS-controlled thyristors (MCTs).
The designers of MOS transistors are often faced with the dilemma of improving the on-resistance of an MOS semiconductor device, while at the same time preventing the device from latching up from the conduction of a parasitic bipolar transistor formed by the source, body and drain regions of the semiconductor device.
This problem was discussed in U.S. Pat. No. 4,860,072 entitled Monolithic Semiconductor Device and Method of Manufacturing Same. The patent disclosed a monolithic semiconductor device for use in various applications such as lateral and vertical MOS transistors, insulated gate conductivity modulated devices and the like, as well as a method of manufacturing same. This device includes source, body and drain regions, with the body region including a channel section which is disposed adjacent an insulated gate formed on the surface of the device. The source region includes a central contact area flanked by a pair of body segments which extend up through the source region and which create a resistive path between the source contact area and the channel section. A voltage is developed across the resistive path which tends to maintain a parasitic bipolar transistor that is formed by the source, body and drain regions in a non-conducting state. A source metallization bridges the two body segments and the intermediate source contact thereby shorting the body region to the source. The geometry of the device is reduced since the contact area need not be increased to ensure that the source metallization contacts the entire source as well as both body segments.
Similarly, in U.S. Pat. No. 4,639,754, a Vertical MOSFET with Diminished Bipolar Effects disclosed an IGFET device that includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body-drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source-body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body-drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions. A source electrode contacts both the body-contact portion and the source region at the wafer surface.
In U.S. Pat. No. 4,495,513 entitled Bipolar Transistor Controlled by Field Effect by Means of an Isolated Gate there is disclosed a bipolar semiconductor structure in which the conductive and blocked states are controlled by an isolated gate. The structure comprises a P+ type substrate constituting the emitter of a bipolar transistor, an N type epitaxial layer constituting the base, a P+ type area having a large surface, constituting a collector, covered with a collector contract and surrounded by an area wherein the epitaxial N type layer is exposed, an N+ type source area included in the collector area and extending along the border of the same so as to define an interval which constitutes the control gate of the structure, a resistive source access zone connected, on the one hand, to the source, and on the other hand, to the collector contact, the resistance of this zone being sufficient for preventing the structure from being rendered conductive in an irreversible manner.
However, none of the devices achieves a interdigitated and/or cellular geometry that allows the optimization of both device on-resistance and ruggedness.
A semiconductor device is disclosed and includes a drain region of a first conductivity type, having a first major surface. Diffused into the drain region is a body region of a second conductivity type. A source region is diffused in the body region and it has a general polygonal shape when viewed at the first major surface with two notches directed towards the center of the source region from opposite sides. The body region is accessible through the notches. An oxide layer covers the source and body regions except for a contact opening position over the source region between the two notches exposing only that portion of the source region that is between the two notches and at least a portion of the accessible body region in each of the two notches to facilitate a source contact.
The polygonal geometry shape with opposing notches in the source and the location of the contact to the source increases the resistance of the source between the channel region and the source contact. This structure lends itself to both cellular and interdigitated configurations. The reduced size of the source contact in conjunction with the two notches in the source allows for a smaller cell size, which in turn allows greater cell density and lowers the overall RDS(on) of the device.